It is common practice to specify the logic description of a CMOS design in a high-level language (such as Verilog or VHDL) and to synthesis this description into a circuit level implementation. Synthesis selects gates from a discrete gate library. It is especially common to synthesis random control logic to reduce the time to develop CMOS designs. Unfortunately synthesized circuit implementations are often slower than a non-synthesized (custom) circuit implementation and these synthesized control logic paths often limit the speed of high-frequency CMOS designs.